Telecom multiplexer for variable rate composite bit stream

ABSTRACT

A multiplexer/demultiplexer (MUX/DEMUX) system for multiplexing and demultiplexing information from a plurality of traffic channels is configured according to a Plesiochronous Digital Hierarchy (PDH) standard into a composite signal transferred to and from a telecommunciations interface. A PDH traffic interface receives PDH channel signals from a plurality of PDH channels and a bit-pipe interface receives bit-pipe traffic transported as a packet data stream. A composite signal generation module and interface then creates, outputs and receives a single composite serial data stream including, in a single composite format, information from the received PDH channel signals as well as the packet data stream. The rate of the bit-pipe traffic may be adaptively modulated as a function of the composite rate.

TECHNICAL FIELD

This invention involves a multiplexer for use in multi-channelcommunications systems that support different formatting protocols.

BACKGROUND

Ever more efficient use of channel bandwidth is a never-ending goal oftelecommunications systems. As technology evolves, from analog signalsover copper wires, to digital wireless and optical fiber networks, sotoo does the bandwidth, and thus both the opportunities and challengesof the problem.

One such challenge arises from the different transport protocols andstandards in use. For example, some protocols (such as the Ethernet)specify asynchronous transmission, while others, such as the SynchronousDigital Hierarchy (SDH) and Synchronous Optical Networking (SONET)standards, rely on tight synchronization. Still other systems aredesigned according to one of the Plesiochronous (from Greekplesio+chronos, meaning “near time”) Digital Hierarchy (PDH) standards,in which different parts of the telecommunications system are almostsynchronised, that is, are synchronized to within some predeterminedacceptable deviation.

Common for these standards is that each specifies transmission of data(including voice data) as a series of “frames” with a fixed framingformat. Some widespread formats are commonly designated T1 (used mostlyin North America and parts of Asia), the faster E1 (2.048 Mbits/s PDHserial bitstream), E2 and E3 (34.368 Mbits/s PDH serial bitstream),formats (used in Europe and most of the rest of the world), as well assome others found mostly in Japan. One result of this, though, is thataccording any one of these framing formats, it is not feasible tocombine, for example, PDH and Ethernet traffic in a single framestructure.

Some attempts to alleviate this problem are themselves part of newerstandards. For example, the Telecommunication Standardization Sector ofthe International Telecommunication Union (ITU-T) has specifiedstandards for multiplexing four E1s into a single E2 in ITU-T Rec.G.742, and for multiplexing four E2s into a single E3 in ITU-T Rec.G.751. Both of these, by definition, set limits on the number of E1 s orE2s that can be transmitted over a composite rate.

United States Published Patent Application No. 2003/0035445 A1,published 20 Feb. 2003 and entitled “Integrated Ethernet andPDH/SDH/SONET Communication System” discloses a communication system forcommunicating Ethernet and PDH/SDH/SONET data using time divisionmultiplexing (TDM) techniques from an Ethernet unit. One drawback ofthis system is that it presupposes an Ethernet unit and a transceiver,with only Ethernet traffic on the packet interface.

U.S. Pat. No. 7,075,952, issued in the name of Torma, et al. on 11 Jul.2005 and entitled “Multiplexing in a PDH Telecommunications Network”specifies a method for multiplexing “at least one traffic source from agroup in which a number of PCM signals constitutes a first trafficsource and a number of packet data streams constitutes a second trafficsource.” The disclosed method is specifically intended for transferringAsynchronous Transfer Mode (ATM) traffic through a PDH network. Onedisadvantage of this method that it operates with a relatively coarsegranularity, at the level of Pulse Code Modulation (PCM) on a firstinterface, which may be as low as 64 kbit/s instead of 2.048 Mbit/s oreven just 1.544 Mbit/s. Another disadvantage is that it requires eachPCM signal to be configured and allocated to a specific portion of theframe; for large frames, this leads to a great deal of configurationdata.

EP 0428407 discloses a communication link in a communication networkwhich dynamically allocates bandwidth to different channels, where atleast three different types of information may be carried by thesechannels. The link carries multiple types of information in amultiplexed manner.

Another drawback of both of these known systems is that they provide nopossibility for adaptive modulation, that is, the rate on the packetstream cannot change without reconfiguration of the frame structure.This lack of flexibility can lead to a needless loss of traffic.

SUMMARY

The invention provides a multiplexer/demultiplexer (MUX/DEMUX) systemfor multiplexing and demultiplexing information from a plurality oftraffic channels configured according to a Plesiochronous DigitalHierarchy (PDH) standard into a composite signal transferred to and froma telecommunciations interface (140). A PDH traffic interface receivesPDH channel signals from a plurality of PDH channels, which may begreater than four in number. A bit-pipe interface receives a bit-pipetraffic data stream. A composite signal generation module and interfaceoutputs and receives a single composite serial data stream including, ina single composite format, information from the received PDH channelsignals as well as the packet data stream.

In one embodiment, the MUX/DEMUX system includes a MUX frame controller;a frame synchronization generator that generates frame syncs for the MUXframe controller; and at least one frame format memory that stores frameformat descriptions.

In cases where the bit-pipe traffic has a variable rate, the MUX framecontroller senses a change in a rate of the composite serial data streamand thereupon changes the capacity of the variable-rate bit-pipeaccordingly, but without changing a frame structure of the compositeserial data stream, thereby adaptively modulating the composite serialdata stream.

The plurality of PDH channels may be configured according to the E1, E2or E3 standards and the bit-pipe traffic data stream may include datatransported as packets, such as Ethernet traffic, or data transportedaccording to a Synchronous Digital Hierarchy (SDH) protocol.

Each frame format description may include a first portion for committeddata and a second portion for any uncommitted data. The composite signalgeneration module and interface may then generate the single compositeserial data stream by sequentially reading the frame format descriptionsfrom the frame format memory, thereby alternately reading and adding tothe single composite serial data stream the first and second portions.In one embodiment, the first portions each store data according to theE1 standard.

The MUX/DEMUX system may be included in a telecommunications system inwhich a basic node creates a plurality of traffic channels. TheMUX/DEMUX then receives the signals to be multiplexed from the basicnode and outputs them to a telecommunications interface, such as awireless (radio) device.

Depending on design choices that skilled telecommunications engineerswill understand, different aspects of different embodiments of theinvention provide various advantages, some of which include:

The multiplexer/demultiplexer, referred to generally as the “Flat MUX”,is non-hierarchical, such that it can multiplex and demultiplex signalsusing a single MUX/DEMUX structure.

Data from different signal sources, according to different standards,may be stored in at least one format memory in a “matrix” representation(row, column) and committed and uncommitted data are transmittedalternately row-by-row. This eliminates the need found in the prior artto transmit all committed data as a block followed by all committed dataas a block. One consequence of this structure is that users can switchfrom the PDH standard to a packet-based standard (Ethernet, SDH, etc.)gradually, with no need to replace or reconfigure hardware.

Prior art, standardized MUXes for multiplexing several E1s into acomposite rate are limited to fixed frame formats. For example, a PDHMUX according to the E1-to-E2 multiplexing scheme specified in the ITU-Tstandard G.742 specifies a format for multiplexing four E1 channels intoone E2 channel. The Flat MUX, however, is more flexible, and sets notheoretical limit on the number of E1s and E3s that it can multiplexinto a single composite signal. Any combination of E1s and E3s is alsopossible, and it is possible to both add and reduce the number of E1sand E3s without disturbing the traffic on the already existing E1s andE3s.

The Flat MUX may also make it possible to include a variable-rate bitpipe in the composite signal.

The Flat MUX supports adaptive modulation, such that if the compositerate changes, the bit-pipe rate will follow the composite rate so thatthe composite payload is most efficiently utilized.

This adaptive ability can, moreover, typically be accomplished withoutintroducing bit faults. Similarly, bit faults are also reduced oreliminated during re-allocation of user bandwidth between PDH channelsand the bit-pipe, at least with respect to the PDH channels not affectedby the reallocation.

Control information may be transported on dedicated channels so as toavoid negatively impacting this utilization. The Flat MUX is alsoparticularly error-tolerant.

The Flat MUX may also reduce the impact of intrinsic jitter and wanderintroduced on PDH rates that are caused by frequency differences betweenthe composite rate and the MUX framing rate.

The Flat MUX has a simple design, which reduces logic consumption.Moreover, the MUX—one exemplifying embodiment of which is discussed indetail—is easily adaptable, for example, to the ANSI standard.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that shows a multiplexer/demultiplexer(MUX/DEMUX) block according to one embodiment of the invention.

FIG. 2 illustrates one example of a composite interface.

FIG. 3 illustrates one example of a suitable timing pattern forcomposite rate data.

FIG. 4 illustrates the general structure of one example of a Flat MUXcontroller in accordance with one embodiment of the invention.

FIG. 5 illustrates one example of logic that can implement a TXfractional divider.

FIG. 6 an example of output timing for a composite clock.

FIG. 7 shows an example of logic used in one embodiment of the inventionto implement frame sync generation.

FIG. 8 illustrates a phase counter with an asynchronous relation betweena system clock and a Transmit (TX) clock.

FIG. 9 illustrates a phase counter in a case in which the TX clock isthe same as the system clock.

FIG. 10 shows the structure of one example of a frame sync phasecounter.

FIG. 11 is a diagram of the state machine structure of a phase counter.

FIG. 12 illustrates one example of a MUX frame control state machine.

FIG. 13 illustrates multi-frame format and stuffing control.

FIG. 14 shows an illustrates an example of MUX control output timing forstuff and unstuff interface operations.

FIG. 15 illustrates a DEMUX frame control state machine.

FIG. 16 illustrates DEMUX control output timing for stuff and unstuffinterface operations.

FIG. 17 illustrates a structure for selective scheduling of either of apair of format memories.

FIG. 18 illustrates format memory ports.

FIG. 19 shows one example of a configuration of a frame header memory.

FIG. 20 shows one example of a configuration of format memory foruncommitted data.

FIG. 21 illustrates a MUX data path delay.

FIG. 22 illustrates a DEMUX data path delay.

FIG. 23 illustrates components of a Wishbone block.

FIGS. 24 and 25 illustrate one example of single-read and single-writetiming diagrams, respectively, for the Wishbone block.

DETAILED DESCRIPTION

For the sake of succinctness, the system and method according to theinvention and disclosed here is referred to as the “Flat MUX” since itis non-hierarchical and can directly multiplex and demultiplex severalE-type channels and/or a configurable number of PDH channels into asingle, composite, serial bit stream, while also making possible avariable bit-pipe of the kind used for packet traffic by using a part ofthe composite bandwidth.

The Flat MUX is of course not intended to exist in isolation, but ratheris a particularly efficient component of an overall telecommunicationssystem that accommodates different channel technologies and framingformats.

Several numerical values are given for various aspects of the embodimentof the invention illustrated and discussed below. These are merelyexample of one practical implementation and can be varied by skilledtelecommunications systems designers according to the needs of a givenimplementation. This applies even to the number of PDH channels the FlatMUX is configured to handle: One advantage of this invention is that theFlat MUX has practically no theoretical limit on the number of PDHchannels it can handle. For example, in one design specification, anembodiment of the invention could support at least 72 E1s or 96 DS1s(another known framing structure) and at least four E3s or 2 DS3sagainst a single basic telecom node.

FIG. 1 is a block diagram that shows a multiplexer/demultiplexer(MUX/DEMUX) block 100 according to one embodiment of the invention, aswell as interfaces to various external components. In FIG. 1, theseinterfaces, named for the signals they transfer, are:

-   -   110: D Control Channel(s) (DCC)    -   112: PDH traffic    -   114: Network Synchronization    -   116: Synchronization Status Message (SSM)    -   118: Bit-pipe signals    -   120: Processor Interface (PIF)    -   122: H Control Channel(s) (HCC)    -   124: Composite signal interface

These various interfaces are preferably co-directional, that is, withboth data and clock signals passing in both directions. The PDHinterfaces are preferably bit oriented. Although not specificallyillustrated, when a Loss of Framing (LOF) signal is detected on thecomposite input 124, an Alarm Indication Signal (AIS) is preferablygenerated on the PDH traffic ports out from the DEMUX circuitry of theunit 100. The AIS is preferably selectable between a local oscillatorand the sync rate of whichever network the invention is implemented in.

An illustrated Basic Node (show to the left of line 150) may include atleast one TDM switch 160, which communicates with the MUX/DEMUX unit viainterfaces 110-116. Between the D Control Channel 110 interface and theTDM switch 160, an additional, but typical, flagstuffing block 170 forrate adaptation is interposed.

A Point-to-Point block 180 is a source of data for the bit-pipe.Communication between the PtP block 180 and the bit-pipe interface 118will generally be necessary for both timing information and I/O data. Inone specified design implementation, 16-bit data was architected forboth receive (RX) input data and transmit (TX) data. Acontra-directional clock (having timing signals with both directions oftransmission directed towards the subordinate equipment) was specifiedas the RX input clock, and an and co-directional clock (clock and datahaving the same source) was specified as the TX output clock.

For both the RX and TX bit-pipe rates, a serial or parallel interfacewas specified to signal the bit-pipe rate and also changes to that rateto the PtP block 180. These rates may be calculated in any known manneras a function of the number of PDH columns used for the bit-pipe.

An acknowledge signal (ACK) was also included to indicate that the PtPblock detected the rate change, as well as conventional signalsindicating various alarm states and loss of framing (LOF). When LOF wasdetected on the composite input 124, and alarm was issued to the PtPblock 180.

Some channels for transporting control information and synchronizationinformation will generally also be needed: The control channels are usedto send control information over the chosen telecom link.Synchronization signals will typically include one like SSM, whichindicates the quality of the synchronization signal, and a networksynchronization signal that is used for transporting synchronizationfrom one side of the link to the other in cases where no synchronizationcarriers are available. Accordingly, according to one specification foran embodiment of the invention, the Flat MUX also supported transport ofat least the following miscellaneous channels:

-   -   Two data communication network (DCN) channels operating against        the Basic Node with a minimum total capacity of 64 kbit/s per        seventh tributary (E1/DS1). The interface was bit-oriented with        both clock and data in both the TX and RX directions.        Contra-directional timing was specified in the TX direction,        that is, the MUX 100 decided the timing. Flag-stuffing (see        component 170) was then used for rate justification between the        incoming DCN channel and the MUX rate, as well as between the        DEMUX rate and the nominal outgoing DCN channel rate.    -   Two HCC channels with approximately 64 kbits total capacity        against an included modem application (shown as a “hitless        switch” 142). The application-to-MUX timing was preferably also        contra-directional.    -   An SSM propagation signal against the Basic Node, one example of        which is a 4-bit wide SSM interface 116 between the MUX 100 and        TDM_SWITCH 160.    -   A network signal propagation channel against the Basic Node;        this may be implemented using the interface 114, which can be        single-bit.

The single composite interface 124 may be implemented against the“hitless switch” modem application or device within a wireless (radio)interface 140—the context of the invention is telecommunications, suchthat the multiplexed and demultiplexed signals are intended for sometelecom device. As is well understood in the art, a “hitless switch” isa device that can switch between different channels, formats, etc.(depending on the context) without inducing or experiencing anysignificant change in signal timing, phase, amplitude, etc. (againdepending on the context).

In this case, the output composite rate from the MUX 100 may be sourcedfrom the modem application, that is, contra-directional timing ispreferably used since the composite rate may change suddenly, albeit itusually in predefined steps, in the presence of adaptive modulation onthe radio interface, which is preferably a byte interface.

One embodiment of the invention also allows for adaptive modulation ratechanges. In such implementations, the interface 124 must also beprovided with some signal for preparing the MUX 100 for such changes.This may be implemented as a one-bit serial interface, where rate andchange information is continuously coded into a serial bit-stream. FIG.2 illustrates one example of the composite interface and FIG. 3illustrates one example of a suitable timing pattern for composite ratedata. In this illustrated example, the Composite Rate (CompRate)interface may consist of a serial clock and data, where the serial bitstream comprises a frame with a frame-alignment word (FAW), a Frequencyfield indicating what the frequency should be, and an End-of-Frame (EOF)field that terminated the field so that false frame alignment can bedetected and avoided.

Some more details of one embodiment of the invention, in particular aFlat MUX controller, will now be explained. As a general matter, theFlat MUX controller is a MUX and DEMUX frame format parser andscheduler. The controller also includes a frame sync generator (FSG) andat least one frame format memory that holds the frame formatdescription. The TX input and the Rx outputs include data trafficchannels such as E1, E3 and PtP data, as well as service channels as DCCand HCC. The TX output and the RX input are composite byte streams toand from the radio interface. These components are shown generally inFIGS. 1 and 2.

FIG. 4 illustrates the general structure of one example of the Flat MUXcontroller 300 according to one embodiment of the invention. As can beseen, this example of Flat MUX control block 300 consists of a MUX and aDEMUX frame control block, 310 and 320, respectively with associatedformat memories 312, 322 (alternatively labelled Format memories A andB, respectively, in the various figures). A frame sync generator 330generates frame syncs for the MUX frame controller. The blocks areconfigured and controlled via a Wishbone bus interface 340, which is aknown interface.

General Structure

In this example, there are four clock domains in the Flat MUX controlblock, which are delimited in FIG. 4 by respective dashed lines:

-   -   1) system clock (clk_sys);    -   2) TX composite clock for the MUX transmit structure        (clk_tx_comp);    -   3) RX composite clock for the DEMUX receive structure        (clk_rx_comp); and    -   4) Wishbone interface clock (clk_wb).        TX Fractional Divider

A TX fractional divider may be included for generating a time base forthe various clock signals. One example of a suitable fractional divideris a numerically controlled oscillator whose function can becharacterized as:

$f_{out} = {{{\frac{Numerator}{Denominator} \cdot {system}}\mspace{14mu}{frequency}} = {\frac{N}{D} \cdot f_{sys}}}$where the output frequency f_(out) is created by accumulating in thenumerator at the system clock rate f_(sys). When the accumulator(nominator) becomes equal to or greater than the value of thedenominator, then the value of the denominator is subtracted from theaccumulator and the clock enable pulse is set during one system clockperiod.

FIG. 5 illustrates one example of logic that can implement the TXfractional divider. As can be seen, the inverted clock enable pulse isgenerated when the accumulator is greater than N+D/2. The numerator isadded to the divided denominator to compensate for the offset that isadded in the accumulator. The multi-frame pulse loads the numerator intothe accumulator registers, which yields a predictable relation in timebetween the frame pulses and the Tx clock enable signal.

Interface

An example of the signal interface for the illustrated TX fractionaldivider is given in Table 1:

TABLE 1 Signal Dir Width Comment clk_sys_rst_n In 1 System reset clk_sysIn 1 System clock MUX tx_num In 16 Tx clock fractional divider numeratortx_denom In 16 Tx clock fractional divider denominator tx_mfp In 1 Txmulti-frame pulse frac_tx_comp_en Out 1 Tx clock enable, rising clockedge frac_tx_comp_en_inv Out 1 Tx clock enable, falling clock edgefrac_tx_comp Out 1 Tx output composite clock

The composite clock may then be generated from the clock enable pulses.An example of the output timing is illustrated in FIG. 6.

Frame Sync Generation (FSG)

In one embodiment of the invention, the frame sync generator 330 intransmitter generates and uses three synchronization signals (syncs) toensure proper frame timing: 1) multi-frame sync (mfs); frame sync (fs);and 3) sub-frame sync (sfs). The syncs may be generated from andtherefore related to the system frequency of the modem 142 transmitter.

The illustrated frame sync generation comprises five counters 431-435,as shown in the example logic illustrated in FIG. 7. The counters may beloaded with counter values from the Wishbone interface, which enables acertain flexibility to use an asymmetric frame structure where thesub-frames may be of different length. The number of frames permulti-frame is also register-controlled. The counters may all loaded atreset, and pulse generated at the release of the system clock resetsignal may be used a as a start signal.

The illustrated counter structure also generates a multi-frame pulse anda frame pulse as shown in FIG. 7. These signals may be one system clockpulse and are used to synchronize data in the system clock domain.

The frame header contains a phase field that is used to realign thephase relation of the composite receive clock and the system clock inthe receiver. The phase counter counts the number of completed systemclock periods between the frame pulse above and a positive edge (forexample) of the composite transmit clock. These relationships areillustrated in FIG. 8, which illustrates a phase counter with anasynchronous relation between the system clock and the TX clock, andFIG. 9, which illustrates the phase counter when the TX clock is thesame as the system clock.

The transmitter composite clock and the system clock may be regarded asasynchronous to each other. The phase relation value may for example becalculated with a counter 702 in the system clock domain and thentransferred to the transmitter clock domain.

Using a structure such as is illustrated in FIG. 10, the frame pulse maybe used to synchronously reset the counter. The frame pulse may thenalso activate a state machine 700 (see also FIG. 11) that may be used tocreate a clock enable pulse to a sample-and-hold register.

A TX clock feedback loop register may be used to generate a signal thatchanges value at the TX composite clock rate. The XOR gate 710 generatesa TX clock enable signal, tx_en, which is synchronous to the systemclock. This pulse is used, according to the state machine, to return tothe idle state and to issue the clock enable pulse as shown in FIG. 11.The clock enable signal is then also transferred to the TX clock domainand there used as a clock enable signal for the phase register. Thephase value parity is calculated using any known logic 720 and added asany predetermined bit.

Interface

An example of the signal interface for the frame sync generation blockis described in Table 2:

TABLE 2 Signal Dir Width Comment clk_sys_rst_n In 1 System reset clk_sysIn 1 System clock MUX clk_tx_comp_rst_n In 1 Tx reset, active lowclk_tx_comp In 1 Tx clock clk_tx_comp_en In 1 Tx clock enable tx_sf0lrIn 16 Tx sub-frame 0 length register tx_sf1lr In 16 Tx sub-frame 1length register tx_sf2lr In 16 Tx sub-frame 2 length register tx_sf3lrIn 16 Tx sub-frame 3 length register tx_mfl In 4 Tx multi-frame lengthtx_mfs Out 1 TX multi-frame sync tx_fs Out 1 Tx frame sync tx_sfs Out 1Tx Sub-frame sync tx_mfp Out 1 Tx multi-frame pulse tx_phase Out 8 Phaseoutput signalMUX Frame Control

The frame control block contains a state machine with sync and framememory format input. The frame parser input may be the same as the framesync signals and the format description of the frame and the body sizehas NROWS rows and NCOLS columns. A functional description of oneexample of the state machine is illustrated in FIG. 12.

The meaning of the parameters in FIG. 12, which is a combined flowchartand state diagram, are either intuitive or are defined in the variousTables. Nonetheless, for convenience, the abbreviations used are:

mfs: multi-frame sync

mem_en memory enable (“_en” generally indicating “enable”)

fs: frame sync

fr_cnt: frame counter

+=1: increment

sfr_cnt: sub-frame counter

format_mem: format memory

format_flag: format flag

stuff_en: enable stuffing

sfs: sub-frame sync

addr: address

header_addr: header address

header_end end of frame header?

body_end end of frame body?

uncom: uncommitted?

ncols: column number

As is well known, the choice of logical state (high or “1” as opposed tolow or “0”) to indicate a given condition is a design choice. Actionsare shown in square brackets (“[ ]”). The state transitions and relatedactions illustrated in FIG. 12 are as follows:

A: mfs=1 [mem_en=1]

B: mfs=0 & fs=1 [fr_cnt+=1] [sfr_cnt=0] [format_mem=format_flag][stuff_en=true]

C: mfs=1 [fr_cnt=0] [sfr_cnt=0] [format_mem=format_flag] [stuff_en=true]

D: mfs=0 & fs=0 & sfs=1 [addr=header_addr] [sfr_cnt+=1]

E: header_end=1 & body_end=1 & uncom=0

F: header_end=0 [addr=header_addr]

G: header_end=1 [addr=header_addr]

H: header_end=1 & ncols=0

I: header_end=1 [addr=body_addr]

J: body_end=1 uncom>0

K: header_end=1 & ncols=0 & uncom=0

L: header_end=1 & body_end=1 & uncom=0

M: body_end=1

N: uncom_end=1

The frame description is divided into three parts: Header, Body andUncommitted data. The frame format is expressed in records, such thateach format record activates the corresponding source and enables thedata path MUX to form the composite data stream.

The state machine is stepped each composite clock cycle to compose thecomposite frame format. The machine is idle in a reset state until thefirst multi-frame sync. The format memories are then enabled forreading.

There are two frame index counters which together are used to set thestart address at the start of each new sub-frame. The sub-frame counteris incremented for each new sub-frame sync and reset at frame sync ormulti-frame sync. The frame sync is incremented for each frame sync andreset by the multi-frame sync. The counters are used to index the startaddress of the format memories for the current frame and sub-frame.

Frame Header

The frame is started with the mandatory frame alignment word and phaseinformation. However, the first data that is inserted into the compositestream at any multi-frame sync, frame sync or sub-frame sync is the LPADregister value. This byte belongs to the previous sub-frame but shouldgenerally always be inserted into the stream previous to the FAW.

The header format memory contains records of the remaining headerinformation and these records are read and executed until the end markis reached for that header. A header record is read and analyzed eachclock cycle with the exception of a DCC or a HCC record, since theserecords contain length fields that will inhibit the header addresscounter for the corresponding number of cycles. In cases where theheader includes only the mandatory fields, conventional header parsingis skipped and the frame parser moves on to the next format description.The parser allows transitions to body data, uncommitted PtP data orpadding.

Frame Body

The body format description contains information about the order inwhich the tributary ports, AIS or the PtP port are to contribute data,whether stuffing is allowed or not, as well as information on how manyof the bytes, for example, rows, that are to contain data in the column.(The remaining rows may contain padding.)

The stuffing procedure may be executed over a multi-frame cycle. Thestuffing is executed by assertion of two signals: Stuffing control andstuffing position. Assertion of the stuffing control signal instructsthe tributary port to insert stuffing control information in the datastream. An assertion of the stuffing position signal informs thetributary that stuffing may be inserted.

FIG. 13 illustrates multi-frame format and stuffing control, in which Kframes F(0), . . . , F(K−2), F(K−1) are illustrated along with timingdiagrams for frame stuffing control and position. In FIG. 13, “C”indicates stuffing control and “P” indicates stuffing position.

The stuffing control signal for the E1 tributary ports is assertedduring the first row in all of the frames but the last frame in themulti-frame. In a similar manner, the stuffing position signal isasserted during the first row of the last frame in the multi-frame. Thestuffing control and position signals are then deasserted during theseintervals if the frame format disallows stuffing for the respectivetributary port.

The number of valid columns and rows are indicated by the NCOLS andNROWS inputs, respectively. The number of columns may vary depending onthe value of a physical mode signal PHY_MODE. A column counter may beused to index the format memory location until a full row is completed,whereupon the column counter is reset and the row counter isincremented. The body records are then parsed until the row counterequals the NROWS input. The valid transitions are to uncommitted data orpadding.

Uncommitted Data

An uncommitted data portion of the format memory 312 may be used tocontain information on the number of additional bytes that are to besent from the PtP bus.

Padding

The last state for each sub-frame is the padding state, where the outputis padded with a PAD register value until one of the three syncsrestarts the frame parser. The syncs are thus treated as synchronousinterrupts. Note that the frame syncs interrupt the frame parserregardless of the present state to maintain the frame synchronization.

Frame Alignment Word (FAW) and Format Memory Switching

The start of a multi-frame or a following frame is determined by theFAW0 and FAW1 combination, for example according to Table 3, in which0=register pattern and 1=inverted. The FAW coding also allows forimmediate frame format switching between the two illustrated formatmemories 312, 322. The format change may be indicated at frame sync ormulti-frame sync by changing the FAW patterns and the parser to switchbetween the format memories. The frame format may not be changed for asub-frame.

TABLE 3 FM FAW0 FAW1 MFAW A 1 1 B 1 0 FAW A 0 1 B 0 0

PtP Traffic

The PtP traffic may be sent either as part of the frame body or asuncommitted data or a combination of both. The frame body formatdescription may include a column record for PtP traffic and informationabout the number of bytes in that column. Stuffing is generally notallowed for PtP traffic so this information bit may be discarded.

The PtP bus requires an estimation of the number of bytes that are sentin the body and as uncommitted data for each sub-frame. This value isdynamic and will vary with the format specifications. The number of PtPbytes in the body may be estimated during the first row at the start ofeach new frame, and this value will be fixed for the remaining of theframe. The number of uncommitted data bytes may be added to this numberat the start of each new sub-frame respectively. Capacity may beestimated according to the following formula:

${{PtP}\mspace{14mu}{Capacity}} = \left\lfloor \frac{{{No}\mspace{14mu}{uncommitted}\mspace{14mu}{data}} + {\sum\limits_{{No}\mspace{14mu}{PtP}\mspace{14mu}{body}\mspace{14mu}{columns}}{{Valid}\mspace{14mu}{bytes}\mspace{14mu}{in}\mspace{14mu}{column}}}}{32} \right\rfloor$

In this example, the capacity estimation output may be an 8-bit unsignedvalue with a resolution of 2048 kbit/s.

Interface

An example of a suitable signal interface is defined in Table 4:

TABLE 4 Signal Dir Width Comment clk_tx_comp_rst_n In 1 Tx reset, activelow clk_tx_comp In 1 Tx clock clk_tx_comp_en In 1 Tx clock enable MUXCONTROL tx_ncols In 8 Number of columns in payload tx_nrows In 8 Numberof rows in payload tx_mfl In 4 Tx multi frame length tx_ff In 1 Frameformat memory register control signal tx_phy_mode In 2 Physical moderegister control signal tx_traffic_mux_ctrl Out 2 Data path MUX controlsignals tx_header_mux_ctrl Out 4 Data path MUX control signals tx_scr_enOut 1 Scrambler enable ptp_cap Out 8 Point-To-Point capacityinformation. The current capacity requirement is indicated in steps of2048 kbit/s, e.g. 0x04 => 10192 kbit/s. ptp_tx_en Out 1 Tx PtP enablesignal FSG tx_mfs In 1 Tx multi frame sync tx_fs In 1 Tx frame synctx_sfs In 1 Tx sub frame sync Stuff stf_tx_ctrl Out 1 Tx stuffingcontrol. A high value indicates that the current output data shallcontain a stuffing control bit. stf_tx_pos Out 1 Tx stuffing position. Ahigh value indicates that the current output data may be used forstuffing. stf_tx_en Out 1 Tx stuffing buffer enable signal stf_tx_selOut 8 Tx stuffing buffer tributary contributor selection signal HCChcc_tx_en Out 1 HCC Tx enable signal hcc_tx_sel Out 2 HCC Tx selectinput, channel 0-3. DCC stf_dcc_tx_stf_en Out 1 DCC Tx stuffing enablesignal 0 - stuffing is disabled 1 - stuffing is enabled dcc_tx_en Out 1DCC Tx data output enable stf_dcc_tx_nsync Out 1 DCC Tx nsync dataoutput enable. A high value indicates that the stuffing buffer shouldsupply a new byte with stuffing information. stf_dcc_tx_sel Out 2 DCC Txchannel selection FORMAT MEMORIES hfm_tx_en Out 1 Tx header formatmemory enable signal hfm_tx_addr Out 9 Tx header format memory addressbus hfm_tx_data_a In 16 Tx header format memory data bus hfm_tx_data_bIn 16 Tx header format memory data bus bfm_tx_en Out 1 Tx body formatmemory enable signal bfm_tx_addr Out 8 Tx body format memory address busbfm_tx_data_a In 16 Tx body format memory data bus bfm_tx_data_b In 16Tx body format memory data bus ufm_tx_en Out 1 Tx uncommitted dataformat memory enable signal ufm_tx_addr Out 7 Tx uncommitted data formatmemory address bus ufm_tx_data_a In 11 Tx uncommitted data format memorydata bus ufm_tx_data_b In 11 Tx uncommitted data format memory data bus

The output signal timing is shown in FIG. 14. The clock in this case isassumed to be faster than the composite clock and the clock enable istherefore only active every sixth clock cycle. Another clock scenario iswhen the clock is the same as the composite clock. The clock enable willin this case be asserted all the time.

DEMUX Frame Control

The DEMUX frame control block implements a state machine with sync andframe memory format input. A functional description of the state machineis shown in FIG. 15. Similar to FIG. 12, the state transitionsillustrated in FIG. 15 are as follows:

A: ais_on=1 [ais_en=1] (ais: Alarm Indication Signal)

B: locked=0

C: mfs=0 & fs=1 [fr_cnt+=1] [sfr_cnt=0] [format_mem=format_flag][stuff_en=true]

D: mfs=1 [fr_cnt=0] [sfr_cnt=0] [format_mem=format_flag] [stuff_en=true]

E: locked=1 & mfs=1 [mem_en=1] [ais_en=0]

F: mfs=0 & fs=0 & sfs=1 [addr=header_addr] [sfr_cnt+=1]

G: header_end=1 & body_end=1 & uncom=0

H: header_end=0 [addr=header_addr]

I: header_end=1 [addr=header_addr]

J: header_end=1 & ncols=0

K: header_end=1 [addr=body_addr]

L: body_end=1 uncom>0

M: header_end=1 & ncols=0 & uncom=0

N: header_end=1 & body_end=1 & uncom=0

O: body_end=1

P: uncom_end=1

The DEMUX frame controller arbitrates the incoming frame data in thesame way as the MUX frame controller with the difference that a RadioProtection Switch (R PS) block decodes the frame alignment and phaseinformation bytes in any suitable manner. The RPS block thereforesupplies the frame syncs and a locked indication that is used to enablethe frame parser. The locked signal is used as a sync valid indicator.Whenever the locked signal is deasserted the frame parser is reset tothe idle state.

The AIS enable signal is asserted when the state machine is the idlestate and the AIS_on registry signal is asserted. The AIS enable signalsets the tributary in AIS mode. The AIS enable signal may also be forcedat any time via a chosen registry bit.

The frame syncs from the RPS are accompanied by a frame format memorysignal. This signal is sampled at frame sync and may at this pointswitch to the whichever of the format memories 312, 322 is currentlyinactive.

Interface

One example of a suitable signal interface is defined in Table 5:

TABLE 5 Signal Dir Width Comment clk_rx_comp_rst_n In 1 Rx resetclk_rx_comp In 1 Rx system clock clk_rx_comp_en In 1 Rx clock enableDEMUX CONTROL rx_ncols In 8 Number of columns in payload rx_nrows In 8Number of rows in payload rx_mfl In 4 Rx multi frame length rx_phy_modeIn 2 Physical mode register control signal rx_ais_mode In 1 AIS mode:0 - Automatic 1 - Manual rx_ais_on In 1 AIS on signal. Controls the AISordering when rx_ais_mode is in manual mode. rx_descr_en Out 1Descrambler enable ptp_rx_en Out 1 Tx PtP enable signal RPS rps_lockedIn 1 Locked signal from RPS rps_rx_mf_sync In 1 Multi frame syncrps_rx_f_sync In 1 Frame sync rps_rx_sf_sync In 1 Sub frame syncrps_rx_ff In 1 Frame format memory control signal STUFF stf_rx_ctrl Out1 Rx stuffing control. A high value indicates that the current datacontains a stuffing control bit. stf_rx_pos Out 1 Rx stuffing position.A high value indicates that the current data contains a data bit orstuffing bit depending on the previous stuffing control bits. stf_rx_enOut 1 Rx stuffing buffer enable signal stf_rx_sel Out 8 Rx stuffingbuffer tributary contributor selection signal stf_rx_ais Out 1 Rx AISgeneration control signal HCC hcc_rx_en Out 1 Produces new COMP_RXoutput for the selected channel. hcc_rx_sel Out 2 HCC Rx select input,channel 0-3. DCC stf_dcc_rx_en Out 1 DCC Rx data enable stf_dcc_rx_nsyncOut 1 DCC Rx nsync data output enable. A high value indicates that thecurrent data contains a stuffing control bit. stf_dcc_rx_sel Out 2 DCCRx channel selection FORMAT MEMORIES hfm_rx_en Out 1 Rx header formatmemory enable signal hfm_rx_addr Out 9 Rx header format memory addressbus hfm_rx_data_a In 16 Rx header format memory data bus from formatmemory A hfm_rx_data_b In 16 Rx header format memory data bus fromformat memory A bfm_rx_en Out 1 Rx body format memory enable signalbfm_rx_addr Out 8 Rx body format memory address bus bfm_rx_data_a In 16Rx body format memory data bus from format memory A bfm_rx_data_b In 16Rx body format memory data bus ufm_rx_en Out 1 Rx uncommitted dataformat memory enable signal ufm_rx_addr Out 7 Rx uncommitted data formatmemory address bus ufm_rx_data_a In 11 Rx uncommitted data format memorydata bus from format memory A ufm_rx_data_b In 11 Rx uncommitted dataformat memory data bus

One example of suitable output signal timing for the DEMUX control blockis illustrated in FIG. 16 and is essentially the same as the timing forthe MUX control: The clock is in this case assumed to be faster thancomposite clock and the clock enable therefore only active every sixthclock cycle. Another clock scenario is when the clock is the same as thecomposite clock. The clock enable will in this case be asserted all thetime.

Format Memory

In the illustrated embodiment, each format memory 312, 322 containsframe format and constitution information. There are thus two identicalmemory banks where two different frame formats may be stored; see FIG.17. In FIG. 17, the components and memory areas marked Wishbone or W arein the domain of the Wishbone clock; those marked M are in the domain ofthe Tx clock; and those marked D are in the domain of the Rx clock.

One advantage of having multiple format memories is that this allows fordynamic frame format switches at the start of a new frame. The frameformats may be stored in the memories via the Wishbone interface 340, bywhich they may also be read.

Each format memory is preferably shared between the MUX and the DEMUX.This implies that three-port asynchronous memories are required. Theillustrated implementation, however, masks two dual-port block RAMmemories as a three-port memory. In the illustrated example, theWishbone interface 340 is the only interface that writes to the memories312, 322, and may write simultaneously to both memories using the samechip select. However, a Read Data port on the Wishbone interface needcontain only data from the MUX memories, as shown in FIG. 18. In FIG.18, memory regions marked M are in the domain of the Tx clock; thosemarked D are in the domain of the Rx clock; and remaining regions andcomponents (including the Wishbone and the regions marked W) are in thedomain of the Wishbone clock.

As illustrated, all of the block RAM address and data outputs arepresent on the MUX and DEMUX port interfaces. This enables simultaneousaccesses, which are required when the header is minimal or it isnecessary to determine the amount of uncommitted data at the end of asub-frame body. Each memory 312, 322 may be provided with a parityencoder and decoder (not shown) such that an interrupt to the Wishboneblock 340 is asserted when a parity error is detected.

Header Memory

The header memory, that is, the memory address space used to store theframe header, contains information of the header, with the exception ofthe mandatory FAW and PHASE records. The memory may be, for example,512×18 bits, of which two out of 18 bits are used for parity. The memorymay be divided into eight 64×16-bit sections, with each section beingassociated with the corresponding frame in a multi-frame. Each sectionmay then be subsequently divided into four 16×16-bit areas of headerrecords, with area corresponding to a sub-frame in that frame. FIG. 19illustrates one possible header memory configuration.

Some form of parity protection is preferably provided for each memory,such that the parity bit(s) is encoded at memory write and decoded atmemory read on either of the two read ports. An interrupt may then beasserted when a parity error is detected by either memory.

Body Memory

The body memory, that is, the memory address space used to store theframe body, may, for example, be 256×18 bits, with, for example, twoparity bits. The body memory contains column records for the frame bodyand each record state a tributary port, valid number of bytes in thatcolumn and a stuffing enable flag. When the stuffing enabled flag isset, stuffing may be inserted in that column. Padding bytes from the PADregister are inserted instead of data when the valid number of bytes isexceeded. As with the header memory, one or more parity bits may beencoded at memory write and decoded at memory read on either of the tworead ports. An interrupt may then be asserted when a parity error isdetected by either memory 312, 322.

Uncommitted Data Memory

The uncommitted data memory, that is, the memory address space used tostore uncommitted data, may be, for example, 128×12 bits, including atleast one parity bit. This memory portion may use the same constitutionas the header memory, with frame sections and sub-frame areas. Each areamay contain several field, for example, four fields, one for eachphysical mode. FIG. 20 illustrates one possible memory configuration foruncommitted data format information. As before, parity may be arrangedsuch that an error is detected by either memory 312, 322.

Interface

One example of a suitable signal interface is defined in Table 6:

TABLE 6 Signal Dir Width Comment WISHBONE clk_wb_rst In 1 Wishbone resetclk_wb In 1 Wishbone clock clk_wb_en In 1 Wishbone clock enable fm_wb_csIn 3 Format memory chip select signals for the Wishbone port interface.One chip select per memory bank: cs0 - Header format memory chip selectcs1 - Body format memory chip select cs2 - Uncommitted PTP memory chipselect fm_wb_we In 2 Format memory write enable signal for the Wishboneport interface fm_wb_addr In 12 Format memory address bus for theWishbone port interface fm_wb_din In 16 Format memory data input bus forthe Wishbone port interface err_mem Out 1 Memory parity error indicationfm_wb_dout Out 16 Format memory data output bus for the Wishbone portinterface MUX clk_tx_comp_rst_n In 1 Tx reset clk_tx_comp In 1 Tx systemclock clk_tx_comp_en In 1 Tx clock enable hfm_tx_en In 1 Tx headerformat memory enable signal hfm_tx_addr In 9 Tx header format memoryaddress bus hfm_tx_data Out 16 Tx header format memory data busbfm_tx_en In 1 Tx body format memory enable signal bfm_tx_addr In 8 Txbody format memory address bus bfm_tx_data Out 16 Tx body format memorydata bus ufm_tx_en In 1 Tx uncommitted data format memory enable signalufm_tx_addr In 7 Tx uncommitted data format memory address busufm_tx_data Out 11 Tx uncommitted data format memory data bus DEMUXclk_rx_comp_rst_n In 1 Rx reset clk_rx_comp In 1 Rx system clockclk_rx_comp_en In 1 Rx clock enable hfm_rx_en In 1 Rx header formatmemory enable signal hfm_rx_addr In 9 Rx header format memory addressbus hfm_rx_data Out 16 Rx header format memory data bus bfm_rx_en In 1Rx body format memory enable signal bfm_rx_addr In 8 Rx body formatmemory address bus bfm_rx_data Out 16 Rx body format memory data busufm_rx_en In 1 Rx uncommitted data format memory enable signalufm_rx_addr In 7 Rx uncommitted data format memory address busufm_rx_data Out 11 Rx uncommitted data format memory data busMUX Data Path

As FIG. 21 illustrates, the MUX data path comprises a MUX 1810 withinthe larger MUX/DEMUX block 100 for traffic data traffic, DCC, PtP dataand padding. This data may be scrambled in a scrambler 1800. A secondMUX 1820 inserts the frame alignment word faw0, faw1, the sub-framealignment word sfaw, and a last padding byte lpad. The MUX controllerrequests data from the various data sources and sets the MUX:es 1810,1820 in the correct state to compose the composite output data. The HCCdata is inserted in a separate MUX 1830 after the MUX data path as HCCis added and after a split point between the primary and redundant datastream.

Scrambler

A scrambler 1840 is preferably included to improve the frequency spectraof the data stream. Some data fields may not be scrambled, however, asthey are used for synchronization in the receiver; consequently, thesebytes are added after the scrambler. The scrambler is preferably haltedduring the insertion of these fields to keep the scrambler and thesubsequent descrambler in sync. The multi-frame sync resets thescrambler to its initial state.

The scrambler 1840 may implement any known algorithm, depending oncriteria that will be well know to telecommunications system designers.In one embodiment of the invention, the scrambler 1840 had threeselectable polynomials:

x²³+x¹⁸+1;

x²⁰+x¹⁷+1; and

x¹⁵+x¹⁴+1,

and it was also made possible to bypass the scrambler/descrambleraltogether simply by setting the scrambler select to zero. The scramblerand descrambler can use the same implementation. The logicalimplementation of such polynomials is well understood.

Interface

According to one design specification of one embodiment of theinvention, the signal interface for the MUX data path block was asillustrated in Table 7:

TABLE 7 Signal Dir Width Comment clk_tx_comp_rst_n In 1 Tx resetclk_tx_comp In 1 Tx system clock clk_tx_comp_en In 1 Tx clock enableWISHBONE tx_faw0 In 8 Tx frame alignment word 0 tx_faw1 In 8 Tx framealignment word 1 tx_sfaw In 8 Tx sub frame alignment word tx_pad In 8 Txdata padding register tx_lpad In 8 Tx last padding tx_scr_bypass In 1Scrambler bypass signal tx_scr_sel In 2 Scrambler polynomial selector00 - x{circumflex over ( )}23 + x{circumflex over ( )}18 + 1 01 -x{circumflex over ( )}15 + x{circumflex over ( )}14 + 1 10 -x{circumflex over ( )}20 + x{circumflex over ( )}17 + 1 11 -x{circumflex over ( )}23 + x{circumflex over ( )}18 + 1 tx_mfs In 1 Txmulti frame sync tx_phase In 8 Phase output signal tx_scr_en In 1Scrambler enable signal. A deasserted enable signal holds the scramblerregisters. tx_traffic_mux_ctrl Out 2 Data path MUX control signalstx_header_mux_ctrl Out 4 Data path MUX control signals stf_txd In 8 Txtributary composite data stf_dcc_txd In 8 Tx DCC composite dataptp_tx_data In 8 Tx Point-To-Point data bus tx_data_comp Out 8 MUXcomposite dataDEMUX Data Path

As FIG. 22 illustrates, the DEMUX 370 comprises a descrambler 2240 andan output register 2250; the names of these components also indicatetheir functions, as will be understood by skilled telecom engineers.

Interface

According to the same design specification mentioned above, the signalinterface for the DEMUX data path block was as illustrated in Table 8:

TABLE 8 Signal Dir Width Comment clk_rx_comp_rst_n In 1 Rx resetclk_rx_comp In 1 Rx system clock clk_rx_comp_en In 1 Rx clock enablerx_descr_bypass In 1 Scrambler enable signal rx_descr_sel In 2 Scramblerpolynomial selector 00 - x{circumflex over ( )}23 + x{circumflex over( )}18 + 1 01 - x{circumflex over ( )}15 + x{circumflex over ( )}14 + 110 - x{circumflex over ( )}20 + x{circumflex over ( )}17 + 1 11 -x{circumflex over ( )}23 + x{circumflex over ( )}18 + 1 rps_rx_mf_syncIn 1 Rx multi frame sync rx_descr_en In 1 Scrambler enable signal. Adeasserted enable signal holds the descrambler registers. rx_data_compIn 8 DEMUX composite data stf_txd Out 8 Rx tributary composite datastf_dcc_rxd Out 8 Rx composite data tributary contributor outputptp_rx_data Out 8 Rx Point-To-Point data busWishbone

As FIG. 23 illustrates, the Wishbone block 340 terminates the Wishboneinterface signals. The block contains a register bank 2310 and aninterface—shown as the Address Decoder 2320—to the format memories 312,322.

The address decoder block 2320 creates chip-select signals that areapplied to the register bank 2310 and the format memories 312 (A) and322 (B). The decoder block 2310 also generates bus termination signalsack_o and err_o at the appropriate time. Read accesses will add a waitstate due to register clocking of the data output bus, but writeaccesses will not require any wait states.

The address decoder 2320, the format memories A and B, and the registerbank 2310 may be clocked with the Wishbone clock. Note that most of thesignals from the register bank 2310 to the various downstream controlblocks are static once the Flat MUX setup is completed.

Table 9 shows a data sheet describing certain aspects of the Wishboneblock 340 according to one design specification of one embodiment of theinvention

TABLE 9 Description Specification Supported cycles SLAVE, READ/WRITEData port, size 16-bit Data port, granularity 16-bit Data port, maxoperand size 16-bit Data transfer ordering Big endian and/or littleendian Data transfer sequencing Undefined Signal name Wishboneequivalent Supported signals list and wb_ack_o ack_o equivalent wishbonesignals. wb_adr_i(15:0) adr_i( ) wb_clk clk_i wb_cyc_i cyc_iwb_dat_i(15:0) dat_i( ) wb_dat_o(15:0) dat_o( ) wb_err_o err_o wb_rstrst_i wb_stb_i stb_i wb_we_i we_i

Table 10 shows an example of the interface signals for the Wishboneblock.

TABLE 10 Signal Dir Width Comment WISHBONE clk_sys_rst_n In 1 Systemreset clk_sys In 1 System clock 131.072 MHz clk_tx_comp_rst_n In 1 Txreset clk_tx_comp In 1 Tx clock clk_tx_comp_en In 1 Tx clock enableclk_rx_comp_rst_n In 1 Rx reset clk_rx_comp In 1 Rx clock clk_rx_comp_enIn 1 Rx clock enable wb_rst In 1 Wishbone reset input wb_clk In 1Wishbone clock input wb_clk_en In 1 Wishbone clock enable input wb_stb_iIn 1 Wishbone strobe input. The strobe input, when asserted, indicatesthat the SLAVE is selected. wb_we_i In 1 Wishbone write enable input.wb_adr_i In 16 Wishbone adress input. wb_dat_i In 16 Wishbone byte datainput. wb_ack_o Out 1 Wishbone Acknowledge output. The acknowledgeoutput, when asserted, indicates the termination of a normal bus cycle.wb_err_o Out 1 Wishbone error output. The error output indicates anabnormal cycle termination. wb_dat_o Out 16 Wishbone byte data output.FORMAT MEMORY fm_wb_dout_a In 16 Format memory data output bus for theWishbone port interface fm_wb_dout_b In 16 Format memory data output busfor the Wishbone port interface fm_wb_cs_a Out 3 Format memory A chipselect signals for the Wishbone port interface. One chip select permemory bank: cs0 - Header format memory A chip select cs1 - Body formatmemory A chip select cs2 - Uncommitted data memory A chip selectfm_wb_cs_b Out 3 Format memory B chip select signals for the Wishboneport interface. One chip select per memory bank: cs0 - Header formatmemory B chip select cs1 - Body format memory B chip select cs2 -Uncommitted data memory B chip select fm_wb_we Out 1 Format memory writeenable signal for the Wishbone port interface fm_wb_addr Out 12 Formatmemory address bus for the Wishbone port interface fm_wb_din Out 16Format memory data input bus for the Wishbone port interface MUXtx_sf0lr Out 16 Tx sub frame 0 length register tx_sf1lr Out 16 Tx subframe 1 length register tx_sf2lr Out 16 Tx sub frame 2 length registertx_sf3lr Out 16 Tx sub frame 3 length register tx_mfl Out 4 Tx multiframe length tx_num Out 16 Tx clock fractional divider numeratortx_denom Out 16 Tx clock fractional divider denominator tx_faw0 Out 8 Txframe alignment word 0 tx_faw1 Out 8 Tx frame alignment word 1 tx_sfawOut 8 Tx sub frame alignment word tx_pad Out 8 Tx data padding registertx_lpad Out 8 Tx last padding tx_ncols Out 8 Number of columns inpayload tx_nrows Out 8 Number of rows in payload tx_ff Out 1 Frameformat memory register control signal tx_phy_mode Out 2 Physical moderegister control signal tx_scr_bypass Out 1 Scrambler enable registersignal tx_scr_sel Out 2 Scrambler polynom select 00 - x{circumflex over( )}23 + x{circumflex over ( )}18 + 1 01 - x{circumflex over ( )}15 +x{circumflex over ( )}14 + 1 10 - x{circumflex over ( )}20 +x{circumflex over ( )}17 + 1 11 - x{circumflex over ( )}23 +x{circumflex over ( )}18 + 1 DEMUX rx_ncols Out 8 Number of columns inpayload rx_nrows Out 8 Number of rows in payload rx_mfl Out 4 Rx multiframe length rx_phy_mode Out 2 Physical mode register control signalrx_descr_bypass Out 1 Scrambler enabler register signal rx_descr_sel Out2 Descrambler polynom select 00 - x{circumflex over ( )}23 +x{circumflex over ( )}18 + 1 01 - x{circumflex over ( )}15 +x{circumflex over ( )}14 + 1 10 - x{circumflex over ( )}20 +x{circumflex over ( )}17 + 1 11 - x{circumflex over ( )}23 +x{circumflex over ( )}18 + 1 rx_ais_mode Out 1 AIS mode: 0 - Automatic1 - Manual rx_ais_on Out 1 AIS on signal. Controls the AIS ordering whenrx_ais_mode is in manual mode. RPS rps_faw0r Out 8 Frame alignment word0 rps_faw1r Out 8 Frame alignment word 1 rps_sfawr Out 8 Sub framealignment word rps_fmfr Out 4 Frames per multi frame registerrps_sf0_len Out 16 Sub frame 0 length register rps_sf1_len Out 16 Subframe 1 length register rps_sf2_len Out 16 Sub frame 2 length registerrps_sf3_len Out 16 Sub frame 3 length register rps_num Out 16 Rx clockfractional divider numerator rps_denom Out 16 Rx clock fractionaldivider denominator stf_tx_fifo_ref Out 8 Tx stuffing buffer FIFO levelreference stf_tx_ais Out 1 Tx AIS generation control signalstf_rx_fifo_ref Out 8 Rx stuffing buffer FIFO level referencestf_dcc_fmfr Out 4 Frames per multi frame register

FIGS. 24 and 25 illustrate one example of single-read and single-writetiming diagrams, respectively, for the Wishbone block 370.

Table 11 lists various signals included in the external interface of oneembodiment of the invention. As with several of the other Tablesincluded above, it is not necessary for an understanding of any aspectof this invention to have a full description of most of the signalslisted in this Table 11. On the other hand, telecommunications engineerswill gain some insight into some of the aspects of one particularspecified design of one implementation of the invention by consideringthese signals in relation to the components into or out of which theypass. Table 11 is thus included here merely for the sake ofcompleteness. Of course, the digital signal widths (in bits), chosenvalues indicating various states (such as 0 or 1), number of paritybits, etc., are all design choices that may be varied according to theneeds of any given implementation of the invention.

TABLE 11 Signal Dir Width Comment Clock clk_sys_rst_n In 1 System resetand clk_sys In 1 System clock reset clk_tx_comp_rst_n In 1 Tx resetclk_tx_comp In 1 Tx system clock clk_tx_comp_en In 1 Tx clock enableclk_rx_comp_rst_n In 1 Rx reset clk_rx_comp In 1 Rx system clockclk_rx_comp_en In 1 Rx clock enable WISHBONE clk_wb_rst In 1 Wishbonereset input clk_wb In 1 Wishbone clock input clk_wb_en In 1 Wishboneclock enable input wb_stb_i In 1 Wishbone strobe input. The strobeinput, when asserted, indicates that the SLAVE is selected. wb_we_i In 1Wishbone write enable input. wb_cyc_i In 1 The cycle input, whenasserted, indicates that a valid bus cycle is in progress wb_adr_i In 16Wishbone adress input. wb_dat_i In 8 Wishbone byte data input. wb_ack_oOut 1 Wishbone Acknowledge output. The acknowledge output, whenasserted, indicates the termination of a normal bus cycle. wb_err_o Out1 Wishbone error output. The error output indicates an abnormal cycletermination. wb_dat_o Out 8 Wishbone byte data output. err_mem_a Out 1Memory parity error indication err_mem_b Out 1 Memory parity errorindication RPS rps_rx_mf_sync In 1 Rx multi frame sync rps_rx_f_sync In1 Rx frame sync rps_rx_sf_sync In 1 Rx sub frame sync rps_rx_ff In 1 Rxframe format rps_locked In 1 Composite frame locked rps_faw0r Out 8Frame alignment word 0 rps_faw1r Out 8 Frame alignment word 1 rps_sfawrOut 8 Sub frame alignment word rps_fmfr Out 4 Frames per multi frameregister rps_sf0_len Out 16 Sub frame 0 length register rps_sf1_len Out16 Sub frame 1 length register rps_sf2_len Out 16 Sub frame 2 lengthregister rps_sf3_len Out 16 Sub frame 3 length register rps_num Out 16Rx clock fractional divider numerator rps_denom Out 16 Rx clockfractional divider denominator STUFF & UNSTUFF BUFFERS stf_txd In 8 Txcomposite data contribution stf_tx_mf_pulse Out 1 Tx multi frame pulse.This signal is used to sample the stuffing FIFO level. stf_tx_ctrl Out 1Tx stuffing control. A high value indicates that the current output datacontains a stuffing control bit. stf_tx_pos Out 1 Tx stuffing position.A high value indicates that the current output data shall insert a databit or stuffing bit depending on the stuff flag. stf_tx_en Out 1 Txstuffing buffer enable signal stf_tx_sel Out 8 Tx stuffing buffertributary contributor selection signal stf_tx_fifo_ref Out 8 Tx stuffingbuffer FIFO level reference stf_tx_ais Out 1 Tx AIS generation controlsignal stf_rx_ctrl Out 1 Rx stuffing control. A high value indicatesthat the current output data contains a stuffing control bit. stf_rx_posOut 1 Rx stuffing position. A high value indicates that the currentoutput data contains a data bit or stuffing bit depending on theprevious stuffing control bits. stf_rx_en Out 1 Rx enable inputstf_rx_sel Out 8 Rx tributary contributor selection signal stf_rxd Out 8Rx composite data tributary contributor output stf_rx_fifo_ref Out 8 Rxstuffing buffer FIFO level reference stf_rx_ais Out 1 Rx AIS generationcontrol signal DCC stf_dcc_txd In 8 DCC Tx composite data contributionstf_dcc_tx_stf_en Out 1 DCC Tx stuffing enable signal 0 - stuffing isdisabled 1 - stuffing is enabled stf_dcc_tx_en Out 1 DCC Tx data outputenable stf_dcc_tx_nsync Out 1 DCC Tx nsync data output enable. A highvalue indicates that the stuffing buffer should supply a new byte withstuffing information. stf_dcc_tx_sel Out 2 DCC Tx channel selectionstf_dcc_rx_stf_en Out 1 DCC Rx stuffing enable signal 0 - stuffing isdisabled 1 - stuffing is enabled dcc_rx_en Out 1 DCC Rx data enablestf_dcc_rx_nsync Out 1 DCC Rx nsync data output enable. A high valueindicates that the current data contains a stuffing control bit.stf_dcc_rx_sel Out 2 DCC Rx channel selection stf_dcc_rxd Out 8 DCC Rxcomposite data tributary contributor output stf_dcc_fmfr Out 4 Framesper multi frame register HCC hcc_tx_en In 1 Produces new COMP_TXnoutput, n is selected by SEL_TX. hcc_tx_sel In 2 HCC Tx select input,channel 0-3. hcc_rx_en Out 1 Indicates that the current input data shallbe used as input for the channel selected by hcc_rx_sel. hcc_rx_sel Out2 HCC Rx select input, channel 0-3. PTP ptp_tx_clk Out 1 TxPoint-To-Point clock output ptp_tx_en Out 1 Tx Point-To-Point clockenable ptp_tx_data In 8 Tx Point-To-Point data bus ptp_rx_clk Out 1 RxPoint-To-Point clock output ptp_rx_en Out 1 Rx Point-To-Point clockenable ptp_rx_data Out 8 Rx Point-To-Point data bus ptp_cap Out 8Point-To-Point capacity information. The current capacity requirement isindicated in steps of 2048 kbit/s, e.g. 0x04 => 10192 kbit/s.tx_data_comp Out 8 MUX composite data frac_tx_comp_en Out 1 Tx clockenable, rising clock edge, generated from internal fractional divider.frac_tx_comp_en_inv Out 1 Tx clock enable, falling clock edge, generatedfrom internal fractional divider. frac_tx_comp Out 1 Tx output compositeclock generated from internal fractional divider. rx_data_comp In 8DEMUX composite dataSome of the advantageous features of the invention include:

The Flat MUX described above has several advantages over the prior art,some or all of which may be implemented in any particular chosenconfiguration of the invention. As already mentioned, beingnon-hierarchical, the Flat MUX can multiplex and demultiplex signalsusing a single MUX/DEMUX structure.

In the embodiment of the invention discussed primarily above, the datafrom different signal sources, according to different standards, may bestored in at least one format memory in a “matrix” representation (row,column). Each “row” included both committed and uncommitted (if any)data and the data is transmitted row-by-row. In other words, committedand uncommitted data is transmitted alternately. This eliminates theneed found in the prior art to transmit all committed data as a blockfollowed by all committed data as a block. One consequence of thisstructure is that users can switch from the PDH standard to apacket-based standard (Ethernet, SDH, etc.) gradually, with no need toreplace or reconfigure hardware.

Prior art, standardized MUXes for multiplexing several E1s into acomposite rate are limited to fixed frame formats. For example, a PDHMUX according to the E1-to-E2 multiplexing scheme specified in the ITU-Tstandard G.742 specifies a format for multiplexing four E1 channels intoone E2 channel. The Flat MUX according to the invention, however, ismuch more flexible, and sets no theoretical limit on the number of E1sand E3s that it can multiplex into a single composite signal. Anycombination of E1s and E3s is also possible, and it is possible to bothadd and reduce the number of E1s and E3s without disturbing the trafficon the already existing E1s and E3s.

One other unique feature of the invention is that it makes it possibleto include a variable-rate bit pipe in the composite signal.

An additional advantage is that the Flat MUX supports adaptivemodulation, such that if the composite rate changes, the bit-pipe ratewill follow the composite rate so that the composite payload is mostefficiently utilized.

This adaptive ability can, moreover, typically be accomplished withoutintroducing bit faults. Similarly, bit faults are also reduced oreliminated during re-allocation of user bandwidth between PDH channelsand the bit-pipe, at least with respect to the PDH channels not affectedby the reallocation.

Note that control information may be transported on dedicated channelsso as to avoid negatively impacting this utilization. The Flat MUX isalso particularly error-tolerant—stuffing control may be designed so asto tolerate on the order of 50 randomly distributed errors under certainconditions.

The Flat MUX also reduced the impact of intrinsic jitter and wanderintroduced on PDH rates that are caused by frequency differences betweenthe composite rate and the MUX framing rate.

Note also that the illustrated embodiment of the MUX itself can carrySSM information.

The illustrated MUX has a simple design, which reduces logicconsumption. Moreover, the MUX—only one exemplifying embodiment of whichis discussed in detail above—is easily adaptable, for example, to theANSI standard.

The invention claimed is:
 1. A multiplexer/demultiplexer (MUX/DEMUX) system for multiplexing and demultiplexing information from a plurality of traffic channels configured according to a Plesiochronous Digital Hierarchy (PDH) standard into a composite signal transferred to and from a telecommunications interface, wherein the system comprises: a PDH traffic interface receiving PDH channel signals from a plurality of PDH channels; a bit-pipe interface receiving a bit-pipe traffic data stream having a variable rate and including data transported as packages; a composite signal generation module and interface that outputs and receives a single composite serial data stream including, in a single composite format, information from the received PDH channel signals as well as the bit-pipe traffic stream; a MUX frame controller; a frame synchronization generator that generates frame syncs for the MUX frame controller; said MUX frame controller being arranged to sense a change in a rate of the composite serial data stream and thereupon being arranged to change the capacity of the variable-rate bit-pipe accordingly, but without changing a frame structure of the composite serial data stream, at least one frame format memory arranged for storing frame format descriptions, each frame format description including a first portion for committed data and a second portion for any uncommitted data, wherein the frame format descriptions are expressed as records, such that each record activates a corresponding source and enables the data path MUX to form the composite data stream the frame format descriptions being stored such that committed and uncommitted data are transmitted alternately; and the composite signal generation module and interface being arranged for generating the single composite serial data stream by sequentially reading the frame format descriptions from the frame format memory, thereby alternately reading and adding to the single composite serial data stream the first and second portions.
 2. The system as defined in claim 1, wherein the plurality of PDH channels comprises more than four PDH channels.
 3. The system as defined in claim 2, wherein the plurality of PDH channels are configured according to the E1, E2 or E3 standards.
 4. The system as defined in claim 1 wherein the bit-pipe traffic data stream includes data transported according to the Ethernet packet-framing standard.
 5. The system as defined in claim 1, wherein the bit-pipe traffic data stream includes data transported according to a Synchronous Digital Hierarchy (SDH) protocol.
 6. The system as defined in claim 1, wherein in that the first portions each store data according to the E1 standard.
 7. A method for multiplexing/demultiplexing (MUX/DEMUX) information from a plurality of traffic channels configured according to a Plesiochronous Digital Hierarchy (PDH) standard into a composite signal transferred to and from a telecommunications interface, where the method comprises the following steps: receiving PDH channel signals from a plurality of PDH channels; receiving a bit-pipe traffic data stream having a variable rate and including data transported as packages; composing, outputting, and receiving a single composite serial data stream including, in a single composite format, information from the received PDH channel signals as well as the packet data stream, storing frame format descriptions in at least one frame format memory; sensing a change in a rate of the composite serial data stream and thereupon changing the capacity of the variable-rate bit-pipe accordingly, but without changing a frame structure of the composite serial data stream, storing frame format descriptions, each frame format description including a first portion for committed data and a second portion for any uncommitted data, wherein the frame format descriptions are expressed as records, such that each record activates a corresponding source and enables the data path MUX to form the composite data stream, the frame format descriptions being stored such that committed and uncommitted data are transmitted alternately; generating the single composite serial data stream by sequentially reading the frame format descriptions from storage, thereby alternately reading and adding to the single composite serial data stream the first and second portions.
 8. The method as defined in claim 7, wherein the plurality of PDH channels comprises more than four PDH channels.
 9. The method as defined in claim 8, wherein the plurality of PDH channels are configured according to the E1, E2 or E3 standards.
 10. The method as defined in claim 7, wherein the bit-pipe traffic data stream includes data transported according to the Ethernet packet-framing standard.
 11. The method as defined in claim 7, wherein the bit-pipe traffic data stream includes data transported according to a Synchronous Digital Hierarchy (SDH) protocol.
 12. The method as defined in claim 7, wherein the first portions each store data according to the E1 standard.
 13. A telecommunications system comprising: a basic node having a plurality of traffic channels, at least one of which is configured according to a Plesiochronous Digital Hierarchy (PDH) standard and at least one other of which comprises a bit-pipe traffic data stream; a telecommunications interface; a multiplexer/demultiplexer (MUX/DEMUX) system for multiplexing and demultiplexing information from the plurality of traffic channels, received from the basic node, into a composite signal that is transferred to and from the telecommunications interface, a PDH traffic interface receiving PDH channel signals from a plurality of PDH channels; a bit-pipe interface receiving a bit-pipe traffic data stream having a variable rate and including data transported as packages; a composite signal generation module and interface that outputs and receives a single composite serial data stream including, in a single composite format, information from the received PDH channel signals as well as the bit-pipe traffic stream; a MUX frame controller; a frame synchronization generator that generates frame syncs for the MUX frame controller; said MUX frame controller being arranged to sense a change in a rate of the composite serial data stream and thereupon being arranged to change the capacity of the variable-rate bit-pipe accordingly, but without changing a frame structure of the composite serial data stream, at least one frame format memory arranged for storing frame format descriptions, each frame format description including a first portion for committed data and a second portion for any uncommitted data, wherein the frame format descriptions are expressed as records, such that each record activates a corresponding source and enables the data path MUX to form the composite data stream, the frame format descriptions being stored such that committed and uncommitted data are transmitted alternately; the composite signal generation module and interface being arranged for generating the single composite serial data stream by sequentially reading the frame format descriptions from the frame format memory, thereby alternately reading and adding to the single composite serial data stream the first and second portions.
 14. The system of claim 1, wherein the plurality of traffic channels comprises more than four PDH channels.
 15. The system as defined in claim 14, wherein the PDH channels are configured according to the E1, E2 or E3 standards.
 16. The system as defined in claim 13, wherein the bit-pipe traffic data stream includes data transported according to the Ethernet packet-framing standard.
 17. The system as defined in claim 13, wherein the bit-pipe traffic data stream includes data transported according to a Synchronous Digital Hierarchy (SDH) protocol. 